[Storage-research-list] CfPart: European Dependable Computing
Conference - EDCC 2020
by Alexander Romanovsky
The 16th European Dependable Computing Conference (EDCC 2020)
September 7-10, 2020
Virtual Event - Call for Participation
http://edcc.dependability.org/
A unique opportunity to learn more about the current work on dependability at no cost!
The European Dependable Computing Conference (EDCC) is a leading venue for presenting and discussing the latest research, industrial practice and innovations in dependable and secure computing. The EDCC is a unique forum for researchers and practitioners to present and discuss their latest research results on theory, techniques, systems, and tools for the design, validation, operation and evaluation of dependable and secure computing systems.
Intel and Fraunhofer IKS are covering the cost of the proceedings and all organisational expenses. Hence, the participation is free of charge. But you will need to register at http://edcc.dependability.org/registration.html.
The EDCC technical program spans over three half days (Sept 8-10, 14h -17h45). It includes three invited talks:
- Towards Universal Safety Guarantees of Decision Making in Automated Vehicles. Ignacio Alvarez. Intel Labs.
- Safety of Autonomous Driving Systems. Alex Haag. AID GmbH.
- Public Transport: Challenges and Opportunities for Dependability. Martin Rothfelder. Siemens AG.
and twenty one technical presentations selected by the Program Committee.
More information about the program could be found here: http://edcc.dependability.org/program.html
Five EDCC workshops are organised on September 7:
- AI4RAILS - 1st International Workshop on Artificial Intelligence for RAILwayS
- DREAMS - Dynamic Risk managEment for Autonomous Systems
- DSOGRI - 2nd International Workshop on Dependable SOlutions for Intelligent Electricity Distribution GRIds
- SERENE - 12th International Workshop on Software Engineering for Resilient Systems
- TAIWAN-DCC - 1st International Workshop on Technology of AI and Wireless Advanced Networking: Dependable Computing and Communication
General chairs:
Michael Paulitsch, Intel
Mario Trapp, Fraunhofer
Program Committee chair:
Elena Troubitsyna, KTH Sweden
Steering Committee chair:
Karama Kanoun, LAAS
Workshop chair:
Simona Bernardi, University of Zaragoza
Publicity chair:
Alexander Romanovsky, Newcastle University
Publication chair:
Miguel Pardal, Universidade de Lisboa
Local Organization chairs:
Veronika Seifried, Fraunhofer IKS
Kerstin Alexander, Intel
For more information, visit:
http://edcc.dependability.org/
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3 years, 3 months
[Storage-research-list] IEEE NVMSA 2020 - Call for Participation
by Sungjin Lee
(Apologies if you receive multiple copies of this message)
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Call for Participation
The 9th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA
2020)
Sokcho, Korea, August 19-21, 2020
https://nvmsa2020.github.io/
NVMSA is a premier conference in the area of non-volatile memory systems and
emerging memory technologies. It provides a fantastic opportunity for global
non-volatile memory researchers from different communities to discuss and
exchange knowledge, ideas and insights, and to facilitate the establishment
of
potential collaborations that can speed up the progress in the design and
application of NVMs.
Since it is an online event, the registration will be completed with full
payment or without payment (free). At least one author is required to
register
for each accepted paper. Other participants can register for free or with
voluntary payment.
We hope to welcome many participants and have lively discussion.
https://nvmsa2020.github.io/registration.html
Preliminary Program Schedule
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* August 19 *
Session 1: Solid-State Drive (13:30-14:30)
NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via
NAND-SPIN (Flash Translation Layer, Wear-Leveling)
Wei-Chun Cheng, Shuo-Han Chen, Yuan-Hao Chang (Academia Sinica), Kuan-Hsun
Chen, Jian-Jia Chen (TU Dortmund), Tseng-Yi Chen (National Central
University), Ming-Chang Yang (The Chinese University of Hong Kong),
Wei-Kuan Shih (National Tsing-Hua University)
High-Performance Solid State Drive with Parallel Read Scheme
Amit Berman (Samsung Electronics)
Session 2: Invited Session I (15:00-16:30)
Pink: High-speed In-storage Key-value Store with Bounded Tails
Jinsu Im, Jinwook Bae (DGIST), Chanwoo Chung, Arvind (MIT), Sungjin Lee
(DGIST)
ATC 2020
AniFilter: Parallel and Failure-Atomic Cuckoo Filter for Non-Volatile
Memories
Hyungjun Oh, Bongki Cho, Changdae Kim, Heejin Park, and Jiwon Seo (Hanyang
University)
Eurosys 2020
Lock-free Concurrent Level Hashing for Persistent Memory
Zhangyu Chen, Yu Hua, Bo Ding, Pengfei Zuo (Huazhong University of Science
and Technology)
ATC 2020
* August 20 *
Session 3: Emerging Technology (08:30-10:00)
FairHym: Improving Inter-Process Fairness on Hybrid Memory Systems
Satoshi Imamura, Eiji Yoshida (Fujitsu Laboratories)
A Kernel Unfolding Approach to Trade Data Movement with Computation Power
for CNN Acceleration
Yueh-Han Wu, Tse-Yuan Wang (National Taiwan University), Yuan-Hao Chang
(Academia Sinica), Tei-Wei Kuo (City University of Hong Kong), and
Hung-Sheng Chang (Macronix)
Exploring Performance Characteristics of ZNS SSDs: Observation and
Implication
Hojin Shin, Myounghoon Oh, Gunhee Choi, Jongmoo Choi (Dankook University)
Session 4: OS and Application (10:30-12:00)
Split’n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing
Christian Hakert, Kuan-Hsun Chen (TU Dortmund), Simon Kuenzer, Sharan
Santhanam (NEC Laboratories Europe GmbH), Shuo-Han Chen, Yuan-Hao Chang
(Academia Sinica), Felipe Huici (NEC Laboratories Europe GmbH), Jian-Jia
Chen (TU Dortmund)
LOCKED-Free Journaling: Improving the Coalescing Degree in EXT4 Journaling
Kyoungho Koo, Yongjun Park (Hanyang University), Youjip Won (KAIST)
A Lightweight Framework for Fast Image Retrieval on Large-Scale Image
Datasets
Renhai Chen, Wenwen Li, Guozheng Rao, Zhiyong Feng (Tianjin University)
Session 5: Energy Optimization (13:30-15:00)
A Zero Energy Consumption Scheme for System Suspend to Limited NVM
Weilan Wang, Liang Shi (East China Normal University), Chun Jason Xue (City
University of Hong Kong), Edwin Sha (East China Normal University)
ScaleML: Machine Learning based Heap Memory Object Scaling Prediction
Joongeon Park, Safdar Jamil, Awais Khan (Sogang University), Sangkeun Lee
(Oak Ridge National Laboratory), Youngjae Kim (Sogang University)
Energy Efficient Approximate Storing of Image Data for MTJ Based
Non-volatile Memory
Yoshinori Ono, Kimiyoshi Usami (Shibaura Institute of Technology)
Session 6: Invited Session II (15:30-17:00)
Evanesco: Architectural Support for Efficient Data Sanitization in Modern
Flash-Based Storage Systems
Myungsuk Kim (Seoul National University), Jisung Park (ETH Zürich and Seoul
National University), Geonhee Cho, Yoona Kim (Seoul National University),
Lois Orosa, Onur Mutlu (ETH Zürich), Jihong Kim (Seoul National University)
ASPLOS 2020
Scalable Parallel Flash Firmware for Many-core Architectures
Jie Zhang, Miryeong Kwon (KAIST), Michael Swift (University of
Wisconsin–Madison), Myoungsoo Jung (KAIST)
FAST 2020
Libnvmmio: Reconstructing Software IO Path with Failure-Atomic
Memory-Mapped Interface
Jungsik Choi, Jaewan Hong (Sungkyunkwan University), Youngjin Kwon (KAIST),
Hwansoo Han (Sungkyunkwan University)
ATC 2020
--------------------------------------------------------------------------------------------------
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3 years, 3 months
[Storage-research-list] [CFP] IA^3 2020 - 10th SC Workshop on
Irregular Applications: Architectures and Algorithms - UPDATED
by Tumeo,
[Please accept our apologies if you receive multiple copies of this message.]
!!!!!!!!!
NEWS: WORKSHOP GOING VIRTUAL; PARCO SPECIAL ISSUE
!!!!!!!!
IA^3 2020
10th Workshop on Irregular Applications: Architectures and Algorithms
http://hpc.pnl.gov/IA3
November 11, 2020
Virtual Workshop
In conjunction with SC20
Sponsored by IEEE TCHPC
--------------------
Call for Papers
--------------------
Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.
Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.
This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:
- Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors
- Network architectures and interconnect (including high-radix networks, optical interconnects)
- Novel memory architectures and designs (including processors-in memory)
- Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing)
- Modeling, simulation and evaluation of novel architectures with irregular workloads
- Innovative algorithmic techniques
- Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
- Impact of irregularity on machine learning approaches
- Parallelization techniques and data structures for irregular workloads
- Data structures combining regular and irregular computations (e.g., attributed graphs)
- Approaches for managing massive unstructured datasets (including streaming data)
- Languages and programming models for irregular workloads
- Library and runtime support for irregular workloads
- Compiler and analysis techniques for irregular workloads
- High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning)
- Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads
Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.
--------------------
Important Dates
--------------------
Abstract Submission: August 28, 2020 (AoE)
Position or Regular Paper Submission: September 4, 2020 (AoE)
Notification: September 28, 2020
Artifact Evaluation: September 28, 2020 - October 10, 2020
Camera-ready: October 10, 2020
Workshop: November 11, 2020
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Submissions
--------------------
Submission site: https://submissions.supercomputing.org
Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references).
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.
The templates are available at:
http://www.ieee.org/conferences_events/conferences/publishing/templates.html.
Accepted papers will be published in the IEEE Digital Library through IEEE TCHPC.
--------------------
Artifact Description & Evaluation
--------------------
This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc20.supercomputing.org/submit/transparency-reproducibility-initi...
Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. Note that differently from the main conferene, this additional page is voluntary (not mandatory - i.e., if a paper has no computational results, do not attach it) for the workshop, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches.
Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared publicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper.
For any additional question on the AD and the AE please contact the Artifact Evaluation Chair, Biagio Cosenza, at bcosenza(a)unisa.it.
--------------------
Special Issue
--------------------
Authors of papers accepted to the workshop will also be invited to submit extended version of their papers to a Special Issue of the journal of Parallel Computing (ParCO) on Hardware/Software Co-design for Sparse and Irregular Applications.
Submissions for the special issue with open December 1, 2020 and will close on March 1, 2021.
For more information on this special issue, please visit the special issue page and/or contact the guest co-editors, Flavio Vella (flavio.vella(a)unibz.it) and Antonino Tumeo (antonino.tumeo(a)pnnl.gov).
https://www.journals.elsevier.com/parallel-computing/call-for-papers/hard...
--------------------
Organizers
--------------------
Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov
John Feo (PNNL), john.feo(a)pnnl.gov
Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov
--------------------
Proceedings Chair
--------------------
Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov
--------------------
Artifact Evaluation Chair
--------------------
Biagio Cosenza (University of Salerno), bcosenza(a)unisa.it
--------------------
Technical Program Committee
--------------------
Nesreen Ahmed, Intel, US
Johnathan Alsop, AMD, US
Eishi Arima, University of Tokyo, JP
Scott Beamer, University of California, Santa Cruz, US
Jonathan Beard, ARM, US
Michela Becchi, North Carolina State University, US
Sanjukta Bhowmick, University of North Texas, US
Erik Boman, SNL, US
David Brooks, Harvard University, US
Prerna Budhkar, Intel, US
Aydin Buluc, LBNL, US
Anastasiia Butko, LBNL, US
Assefaw Gebremedhin, Washington State University, US
Cat Graves, HPE, US
Rajiv Gupta, University of California, Riverside, US
Peter M. Kogge, Notre Dame University, US
John Leidel, Tactical Computing Lab, US
Kamesh Madduri, Pennsylvania State University
José Moreira, IBM Research, US
Miquel Moretó, Barçelona Supercomputing Center, ES
Maxim Naumov, Facebook, US
Fanny Nina-Paravecino, Microsoft, US
Roger Pearce, LLNL, US
Keshav Pingali, University of Texas, Austin, US
Alejandro Rico, ARM, US
Jason Riedy, Georgia Tech, US
Thomas B. Rolinger, University of Maryland, US
Kentaro Sano, RIKEN, JP
John Shalf, LBNL, US
Shaden Smith, Microsoft, US
Tyler Sorensen, University of California, Santa Cruz, US
Ruud van der Pas, Oracle, NL
Ana Lucia Varbanescu, University of Amsterdam, NL
Flavio Vella, Free University of Bozen, IT
Other members TBD
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