[Please accept our apologies if you receive multiple copies of this message.] !!!!!!!!! NEWS: WORKSHOP GOING VIRTUAL; PARCO SPECIAL ISSUE !!!!!!!! IA^3 2020 10th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 November 11, 2020 Virtual Workshop In conjunction with SC20 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning) - Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: August 28, 2020 (AoE) Position or Regular Paper Submission: September 4, 2020 (AoE) Notification: September 28, 2020 Artifact Evaluation: September 28, 2020 - October 10, 2020 Camera-ready: October 10, 2020 Workshop: November 11, 2020 -------------------- Submissions -------------------- Submission site: https://submissions.supercomputing.org Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references). Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Accepted papers will be published in the IEEE Digital Library through IEEE TCHPC. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc20.supercomputing.org/submit/transparency-reproducibility-initi... Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. Note that differently from the main conferene, this additional page is voluntary (not mandatory - i.e., if a paper has no computational results, do not attach it) for the workshop, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared publicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair, Biagio Cosenza, at bcosenza(a)unisa.it. -------------------- Special Issue -------------------- Authors of papers accepted to the workshop will also be invited to submit extended version of their papers to a Special Issue of the journal of Parallel Computing (ParCO) on Hardware/Software Co-design for Sparse and Irregular Applications. Submissions for the special issue with open December 1, 2020 and will close on March 1, 2021. For more information on this special issue, please visit the special issue page and/or contact the guest co-editors, Flavio Vella (flavio.vella(a)unibz.it) and Antonino Tumeo (antonino.tumeo(a)pnnl.gov). https://www.journals.elsevier.com/parallel-computing/call-for-papers/hard... -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov John Feo (PNNL), john.feo(a)pnnl.gov Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov -------------------- Artifact Evaluation Chair -------------------- Biagio Cosenza (University of Salerno), bcosenza(a)unisa.it -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Johnathan Alsop, AMD, US Eishi Arima, University of Tokyo, JP Scott Beamer, University of California, Santa Cruz, US Jonathan Beard, ARM, US Michela Becchi, North Carolina State University, US Sanjukta Bhowmick, University of North Texas, US Erik Boman, SNL, US David Brooks, Harvard University, US Prerna Budhkar, Intel, US Aydin Buluc, LBNL, US Anastasiia Butko, LBNL, US Assefaw Gebremedhin, Washington State University, US Cat Graves, HPE, US Rajiv Gupta, University of California, Riverside, US Peter M. Kogge, Notre Dame University, US John Leidel, Tactical Computing Lab, US Kamesh Madduri, Pennsylvania State University José Moreira, IBM Research, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Microsoft, US Roger Pearce, LLNL, US Keshav Pingali, University of Texas, Austin, US Alejandro Rico, ARM, US Jason Riedy, Georgia Tech, US Thomas B. Rolinger, University of Maryland, US Kentaro Sano, RIKEN, JP John Shalf, LBNL, US Shaden Smith, Microsoft, US Tyler Sorensen, University of California, Santa Cruz, US Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Flavio Vella, Free University of Bozen, IT Other members TBD _______________________________________________ Storage-research-list mailing list Storage-research-list(a)ece.cmu.edu https://lists.andrew.cmu.edu/mailman/listinfo/storage-research-list